IIT Bombay Campus, by , under Creative Commons license.
Schedule
| Dec-8 Day 1 | Dec-9 Day 2 | Dec-10 Day 3 | |
|---|---|---|---|
| 09:00 -- 10:30 | Scaling up SAT+SMT to Industry ProblemsR. Venkatesh | SAT Solvers, CDCL and ProofsMate Soos | From clauses to pseudo-Boolean constraints in a Boolean solverDaniel Le Berre |
| 10:30 -- 11:00 | Coffee Break | ||
| 11:00 -- 12:30 | UCLID5: Integrating Modeling, Verification, Synthesis, and LearningSanjit A. Seshia | SAT Solving and CDCL(T)Mate Soos | From satisfaction to optimization, and beyondDaniel Le Berre |
| 12:30 -- 14:00 | Lunch | ||
| 14:00 -- 15:30 | Towards Verified AI with VerifAI and ScenicSanjit A. Seshia | SAT Solving and CDCL(T) -- Hands onMate Soos | Sat4j practical sessionDaniel Le Berre |
| 15:30 -- 16:00 | Coffee Break | ||
| 16:00 -- 16:40 | Validating optimizations of concurrent C/C++ programsSoham Chakraborty | Knowledge Compilation for Boolean Functional SynthesisSupratik Chakraborty | A stroll inside Z3Ashutosh Gupta |
| 16:40 -- 17:20 | Approximation Strategies for Incomplete MaxSATSaurabh Joshi | Quantitative Verification of Neural NetworkKuldeep S. Meel | General Assembly-- |
| 17:20 -- 18:00 | Poster Session | -- | |