SAT + SMT

	Dec-8 Day 1	Dec-9 Day 2	Dec-10 Day 3
09:00 -- 10:30	Scaling up SAT+SMT to Industry Problems R. Venkatesh	SAT Solvers, CDCL and Proofs Mate Soos	From clauses to pseudo-Boolean constraints in a Boolean solver Daniel Le Berre
10:30 -- 11:00	Coffee Break
11:00 -- 12:30	UCLID5: Integrating Modeling, Verification, Synthesis, and Learning Sanjit A. Seshia	SAT Solving and CDCL(T) Mate Soos	From satisfaction to optimization, and beyond Daniel Le Berre
12:30 -- 14:00	Lunch
14:00 -- 15:30	Towards Verified AI with VerifAI and Scenic Sanjit A. Seshia	SAT Solving and CDCL(T) -- Hands on Mate Soos	Sat4j practical session Daniel Le Berre
15:30 -- 16:00	Coffee Break
16:00 -- 16:40	Validating optimizations of concurrent C/C++ programs Soham Chakraborty	Knowledge Compilation for Boolean Functional Synthesis Supratik Chakraborty	A stroll inside Z3 Ashutosh Gupta
16:40 -- 17:20	Approximation Strategies for Incomplete MaxSAT Saurabh Joshi	Quantitative Verification of Neural Network Kuldeep S. Meel	General Assembly --
17:20 -- 18:00	Poster Session	--